The downscaling of the dimensions of ICs such as CMOS ICs continually poses IC designers with difficult design challenges, not in the least because the reduction in feature size is usually accompanied by a demand for the integration of a higher number of components in the IC. Typically, this makes it increasingly difficult to ensure that all semiconductor components of the IC can be properly connected to the metal layers of the IC. In addition, the reduction of the feature size of a building block of the IC such as a transistor must be achieved whilst ensuring that the performance of the transistor or at least the overall performance of the IC is not adversely affected. It will be obvious that the above challenges are by no means trivial.
For instance, it is difficult to achieve a compact power transistor, since such a transistor typically has to provide a high power output, for which a low-resistive channel is required. This may be achieved by increasing the dimensions of the channel and by placing strips of the source (S), drain (D) and channel (C) regions in parallel in an interdigited fashion, e.g. SCDCSCDC . . . . However, such a layout is not particularly area-efficient and requires interdigited metal structures for connecting these transistor regions, which cannot be automatically routed due to their complexity, thus adding to the complexity and cost of the design.
An improved layout is disclosed in US 2006/0238241. This patent application discloses a QVDMOS transistor comprising a checkerboard pattern of source and drain regions, wherein the source and drain regions are separated from each other by a grid of gate regions. This improves the effective channel width of the transistor, but complicates the interconnection of the transistor regions to the metal layers of the IC, as indicated in US 2006/0238241. Moreover, a further problem is that the area-efficient checkerboard layout of the source and drain regions makes it more difficult to provide additional contacts to the substrate. This is particularly relevant in CMOS technology where contacts to the substrate are required to prevent latch-up. Additional contacts may be provided in the periphery of the transistor but this has the disadvantage that a relatively large number of contacts is required to provide satisfactory protection against latch-up, thereby off-setting the area gains achieved by the checkerboard layout.